面向并行工程的电子系统测试性建模方法与技术

项目名称： 面向并行工程的电子系统测试性建模方法与技术

项目编号： No.61201009

项目类型： 青年科学基金项目

立项/批准年度： 2013

项目学科： 电子学与信息系统

项目作者： 杨成林

作者单位： 电子科技大学

项目金额： 27万元

中文摘要： 测试性模型自动化生成问题是复杂电子系统测试性设计的核心问题，也是公认的难题。主要原因有三方面：一是缺乏有效的测试性模型描述方法，该方法应能对方案设计、初步设计和详细设计等各阶段系统测试性模型进行描述；二是没有一种由系统信息自动生成测试性模型的方法；三是缺乏高效的级间模型信息传递途径和更新算法。针对这三方面的问题，将研究以下几方面内容：以故障模式-功能依赖关系为基础，研究层次化模型描述方法；搭建模型信息交互框架，利用信息论、图论和矩阵论推导模型生成方法；以时间复杂度最低为目标，研究级间模型信息更新和模型重构的高效算法。希望在电子系统测试性自动化建模方面有所突破，使得测试性模型能够随系统设计和使用全周期自动生成、更新和完善，满足并行工程下对测试性设计"尽早开展、全周期融入、有关活动并行交叉"的要求，为在研电子系统测试性设计提供科学方法和技术支撑，切实推进测试性设计实用化进程。

中文关键词： 测试性；测试性设计；测试性建模；优化；

英文摘要： Automatic testability modeling is the core issue of Design for Testability (DFT) for electronic system and is widely recognized as a challenge. There are three main reasons: 1. There is no suitable model representation method which can model a system during any phase of design, such as conceptual design phase, schematic design phase and design development phase. 2.There is no automatic testability modeling method. 3. The lack of effective model information updating algorithm. Aiming at these problems, the following issues are researched. Based on fault model-function dependency, a hierarchical model representation method is researched at first. Then, model information interchange frame is constructed, and method of automatic modeling is researched based on information theory, graph theory and matrix theory. Finally, to achieve the lowest time complexity, an effective model information updating algorithm is researched. The aim is to break through some bottleneck issues in the automatic testability modeling method and make sure that the testability model can be automatically generated, updated and mature through out the whole design phases. This research can achieve the "be deployed as early as possible and merged into the whole design-cycle, DFT-correlative mission deployed in a parallel-cross style" needs of con

英文关键词： testability；design for testability；testability modeling；optimization；