面向高带宽应用的高速串行接口电路关键技术研究

项目名称： 面向高带宽应用的高速串行接口电路关键技术研究

项目编号： No.61474134

项目类型： 面上项目

立项/批准年度： 2015

项目学科： 无线电电子学、电信技术

项目作者： 张锋

作者单位： 中国科学院微电子研究所

项目金额： 93万元

中文摘要： 随着大数据时代的到来，数据吞吐率急速增加，从而对数据传输接口的带宽要求越来越高，因此，高速接口电路成为了制约芯片数据传输能力的关键因素。本课题将重点关注超高速接口的集成电路设计实现技术，通过以100Gb传输带宽为目标来构建完整的接口系统及电路模型，旨在解决超高速接口电路中一系列关键问题。本课题在实现该系统的同时，还要重点对25Gb/s高速发送器电路的低功耗实现技术、25Gb/s高速时钟数据恢复电路的信号跟踪技术、25Gb/s连续时间与判决反馈的混合均衡电路技术、25Gb/s高速时钟锁相环电路的反馈锁定技术以及100Gb带宽多通道接口系统电路的信道匹配技术等展开研究，将通过电路设计、流片验证及测试等方法对超高速接口电路的关键技术进行探索，最终解决我国高速接口芯片设计中的若干技术难题，进而满足对高速接口的迫切要求，并且取得具有我国自主知识产权的一系列研究成果。

中文关键词： 超高速串行接口电路；低功耗源终端发送器；高速时钟电路；时钟数据恢复电路；均衡器

英文摘要： With the advent of Big Data era and the rapidly increasing in data throughput, there has been a huge growth in serial interface bandwidth requirements. However, the design of high-speed interface circuit architectures place severe constraints on the data transmission capacity. In order to resolve many key issues in realizing the ultra high-speed interface circuits, this project will target on the interface circuit design and implementation to build a complete interface system and circuit model by investigating the data rate of 100Gb/s transmission. The project can achieve the system while simultaneously focusing on the research of 25Gb/s high-speed clock and data recovery circuit signal tracking technology, 25Gb/s continuous time and hybrid decision feedback equalization circuit technology, 25Gb/s high-speed phase-locked loop circuit feedback locking technology, and 100Gb/s multi-channel interface system circuit channel matching technology. We will probe deeply into the ultra high-speed significant topology through the circuit design, chip test and validating the entire process. Thus, the ultimate goal of the project is to provide the solution for several technical challenges in designing interface chips, and meet the urgent demand for high-speed serial interfaces, which expects to obtain a series of research results with our own intellectual property rights.

英文关键词： Ultra-high Speed Serdes;Low power SST;High Speed Clock;Clock and Data Recovery;Equalizer