高性能CPU中动态逻辑电路的低功耗方法学研究

项目名称： 高性能CPU中动态逻辑电路的低功耗方法学研究

项目编号： No.61204040

项目类型： 青年科学基金项目

立项/批准年度： 2013

项目学科： 信息四处

项目作者： 汪金辉

作者单位： 北京工业大学

项目金额： 24万元

中文摘要： 动态逻辑电路以速度快、版图面积小的优良特性被广泛应用于CPU的数据通路和片上存储器（Caches，Register Files等）中。然而，随着集成电路工艺的不断发展，动态逻辑电路过高的功耗已成为高性能CPU的设计瓶颈。本项目分别对数据通路和片上存储器中的动态逻辑电路提出低功耗解决方案。具体内容包括：1. 提出电荷复用技术来优化Zipper动态逻辑电路，并基于最优部件选择模型，实现低功耗数据通路的设计；2. 研究片上存储器动态位线的最佳休眠矢量的选取，考虑应用需求、电路设计参数、制造工艺、PVT浮动、老化效应、休眠时间等多个重要因素的影响，使休眠动态位线产生最小的泄漏电流，同时提出Clock Biased技术，在提高位线运算速度的同时，有效的降低功耗，进而完成低功耗片上存储器的设计。项目的研究成果，对于我国开发具有自主知识产权的低功耗、高性能CPU具有重要的理论价值和实际应用意义。

中文关键词： 动态逻辑电路；微处理器；片上存储器；低功耗；

英文摘要： Dynamic logic circuits are widely applied in data path and on-chip memory (such as Caches, Register Files) of modern CPU due to the superior speed and area characteristics. However, with the development of IC technology, the high power comsumption of dynamic logic circuit has become one of the primary design constraints in high performance CPU. This project focus on low power solutions for dynamic circuits in both data path and on-chip memory, respectively. The research contents in this project are as follows: 1. The charge recycle technique is proposed to optimize the Zipper dynamic circuits. Combined with a new component selected model, low power date path design is achieved; 2. The optimum sleep vector of dynamic bit-line in on-chip memory is investigated to minimze the leakage power, while taking into account multiple important factors including application cases, design parameters, manufacturing technologies, PVT variations, aging effect, and standby interval. In addition, a novel Clock Biased technique is presented for on-chip memory to enhance the access speed and reduce the power simultaneously. The result of this project can greatly contribute to developing low power and high performance CPU with independent intellectual property right in China.

英文关键词： Dynamic logic；Microprocessor；On-chip memory；Low power；