高速系统PDN瞬态噪声的时域分析与非线性抑制技术

项目名称： 高速系统PDN瞬态噪声的时域分析与非线性抑制技术

项目编号： No.61501345

项目类型： 青年科学基金项目

立项/批准年度： 2016

项目学科： 无线电电子学、电信技术

项目作者： 刘洋

作者单位： 西安电子科技大学

项目金额： 19万元

中文摘要： 数字IC进入亚微米/纳米工艺后，高速系统的时钟主频达数GHz，工作电压降至1V以下，瞬态电流却飙升到50A/ns，引发电源分配网络(PDN)中的电源/信号电压瞬态噪声及派生的时序抖动严重超标。目前业界惯用的基于频域目标阻抗的电源分配网络设计准则在高频段已呈现瓶颈，导致采用合理的封装和去耦资源难以满足系统对噪声和抖动的要求。面对挑战，本项目将在时域对电源最差瞬态噪声激励源模式进行理论分析，研究指导电源分配网络设计的新理论依据和临界条件；同时，基于电路敏感度理论分析电源分配网络，提出采用有源电阻进行电源瞬态噪声的非线性抑制技术；然后，研究电压噪声幅度和频谱与系统时序抖动响应关系，提出统一规划电压噪声预算和时序抖动预算的电源分配网络优化设计方法。最终实现对电源分配网络、时钟分配网络及信号线网的协同设计。研究成果可用于指导当代高速高密度数字系统及芯片电源分配网络的设计。

中文关键词： 电源分配网络；时域瞬态噪声；电源引发抖动；电路敏感度；非线性抑制

英文摘要： As the size of the IC technology shrinks to submicron/nanometer, the clock rate reaches up to several GHz, and the working voltage decreases to less than 1V while the transient current can soar to even 50A/ns in the high-speed system, which makes the power/signal voltage transient noise and its induced timing jitter in power delivery network (PDN) exceed the tolerance heavily. The present PDN design methodology based on frequency domain target impedance which is most widely adopted in industry appears inaccurate in high frequency domain, so it is difficult to achieve the requirements for voltage noise and timing jitter of the high-speed system by using reasonable package and decoupling resources. For above challenges, the stimuli mode of current source which can produce the worst-case voltage noise for the PDN will be theoretically analyzed in time domain, and the new theoretical basis and critical criteria for the PDN design will be investigated in this project. Simultaneously, the circuit sensitivity theory will be used to analyze the PDN, and the non-linear suppression technology for power transient noise by using active resistor will be proposed. Subsequently, the relationship between the amplitude and spectrum of voltage noise and the timing jitter of the system will be investigated, and the PDN optimization method is proposed for considering the voltage noise and the timing jitter simultaneously. Ultimately, the co-design for the PDN, clock distribution network and transmission line network will be achieved. The research results of the project can provide the guideline for the analysis and design of high-speed and high-density digital system and chip.

英文关键词： Power Delivery Network;Time-Domain Transient Noise;Power Supply Induced Jitter;Circuit Sensitivity;Non-linear Suppression