三维视频处理系统芯片动态可重构可编程体系结构研究

项目名称： 三维视频处理系统芯片动态可重构可编程体系结构研究

项目编号： No.61272120

项目类型： 面上项目

立项/批准年度： 2013

项目学科： 自动化技术、计算机技术

项目作者： 蒋林

作者单位： 西安邮电大学

项目金额： 80万元

中文摘要： 以多点视频压缩编码为代表的三维视频处理，是高清视频实时通信系统的关键技术。多视点和高分辨率编解码，对视频处理SoC的计算能力和编程灵活性提出了更高的要求。芯片集成度的提高，又使处理器体系结构设计面临长线、功耗与工艺缺陷等红墙问题。项目面向三维视频阵列SoC，尝试采用大量同构、规则处理器元邻接互连的思想，探索建立适应未来制造工艺发展的动态可重构可编程结构，不仅支持MVC、H.264/AVC和AVS等多种视频压缩标准，还可同时实现细粒度的大规模并行指令流计算（比特流解析、VLD等）和并行数据流计算（DCT、ME等）。研究处理器元及其互连结构、阵列处理器指令集架构和片上存储结构，预期提出的统一体系结构和开发的原型系统，既具有编程的灵活性又能通过重构达到ASIC/FPGA等专用硬件的性能。项目将为下一代片上系统体系结构研究提供新的思路，推动任意视点视频、三维电视和虚拟现实等新兴多媒体应用的发展。

中文关键词： 阵列处理器；可重构计算；体系结构建模；编解码；三维视频

英文摘要： 3D video processing is the key technology in real-time communication system of high definition video, which takes multi-view video compression coding as criteria. The coding and decoding of multi-view and high resolution video require high computing performance and programming flexibility for video processor. With the increasing density of chip integration, the red-wall issues, such as long-wire, power dissipation and process defect, challenge the architecture design. This project will study the application of 3D video, explore a novel AP architecture which accommodates the process development and support multiple video compression standards, such as MVC, H.264/AVC and AVS, also implements finegrained computing of massive parallel instruction stream and data stream, with massive homogenous, regular processor elements connected locally. We will investigate processing element architecture and its interconnect of array processor, the instruction set architecture and storage structure of array processor. The proposed architecture and its prototyping system can obtain both the flexibility of programming and high performance of ASIC/FPGA. The achievements will provide new direction for next-generation SoC architecture design, bring the development of emerging multi-media applications, such as free-view video, 3D TV,

英文关键词： Array Processor；Reconfigurable Computing；Architecture Modeling；Coding/Decoding；3D Video