面向同质三维集成应用的硅纳米线器件技术研究

项目名称： 面向同质三维集成应用的硅纳米线器件技术研究

项目编号： No.61474004

项目类型： 面上项目

立项/批准年度： 2015

项目学科： 无线电电子学、电信技术

项目作者： 黎明

作者单位： 北京大学

项目金额： 76万元

中文摘要： 随着CMOS大规模集成电路技术逼近尺寸缩小的极限，二维平面上的集成规模难以进一步提升，未来集成电路架构将朝着三维集成和系统集成的方向发展。不同于TSV三维集成技术，本项目提出采用同质三维集成的方法，将不同功能的硅纳米线器件在第三维度的不同层次上集成起来，以突破传统平面集成电路技术的集成度瓶颈。本项目拟针对纳米线器件在同质三维集成应用方面所面临的三类主要科学问题和技术困难展开研究：1）纳米线沟道材料特性对三维同质集成器件的输运特性的影响；2）热预算对同质三维集成中不同层次器件性能的影响；3）同质三维集成中不同层源漏的非本征寄生效应。针对上述问题和技术难点，本项目拟采用工艺试制和理论模型相结合的方法，开展材料工艺、集成工艺、工艺模型和器件表征等研究，最终提出纳米线器件的同质三维集成方案，为延续CMOS集成电路摩尔定律提供创新的方法。

中文关键词： 场效应晶体管；硅纳米线器件；同质三维集成；半导体材料；仿真

英文摘要： As CMOS VLSI technology approaches the downscaling limit, the integration level on 2-dimensional plane becomes hard to be raised. To increase IC density and reduce cost, the future IC architecture will be developed along the 3-dimensional integration direction. Not like TSV technology for 3D integration, this project proposes homogeneous 3D integration method to fabricate the different functional silicon nanowire transistors on the multilayers at the Z-direction, so as to break the density bottleneck of traditional VLSI technology. To do that, this project will try to solve three major science and technique problems as follows: 1) the effect of channel material on the transport of homogenously integrated nanowire transistors;2) the impact of thermal budget on the multilayer devices homogeneously integrated; 3) the parasitic effect of source/drain contact of multilayer devices. Aiming at the above problems and issues, this project intends to employ the combined method of process fabrication and theoretical modeling to carry out the research on new material, process integration, process modeling and device characterization. As a final result, a homogeneous 3-dimensional integration solution for nanowire transistors will be proposed to provide an innovative method to extend the life of Moore's law of CMOS VLSI technology.

英文关键词： MOSFET;silicon nanowire device;homogeneous 3-dimensional integration;semiconductor material;simulation