项目名称: 多通道时间交织逐次逼近ADC高层次模型及关键技术研究
项目编号: No.61204029
项目类型: 青年科学基金项目
立项/批准年度: 2013
项目学科: 信息四处
项目作者: 佟星元
作者单位: 西安邮电大学
项目金额: 31万元
中文摘要: 随着集成电路设计技术和工艺的进步,多通道时间交织逐次逼近(SAR)ADC已经成为纳米级低功耗SoC中很有前景的高速ADC结构,而内部关键器件以及各通道间的匹配性是限制其性能的瓶颈。本项目在申请人前期获得的SAR ADC高层次匹配模型及能耗模型的指导下对SAR ADC进行匹配性和功耗优化,提出一种结合全单位电容阵列和电阻梯间歇工作模式的新型D/A转换网络以及一种基于自调节技术的低功耗逻辑控制方式,在此基础上采用多通道时间交织技术提高SAR ADC采样速率,建立多通道时间交织SAR ADC的高层次系统模型,该模型能够准确反映关键器件匹配误差以及各通道在带宽、采样时间、增益、失调、非线性等方面的匹配误差与整体ADC性能之间的定量关系,最后以该模型为指导,获得多通道时间交织SAR ADC在匹配性和功耗方面的优化设计技术。本项目能够为A/D转换器的设计优化提供理论指导,提高国内数据转换器设计水平。
中文关键词: 模数转换器;逐次逼近;高层次模型;时间交织;低功耗
英文摘要: With the improvement of circuit design and technology, the time-interleaved successive-approximation-register A/D converters (SAR ADCs) have recently become very attractive in the nanoscale CMOS low power SoCs. However, the mismatches between the internal key components and that between the channels can degrade the overall performance of the time-interleaved SAR ADCs. In this program, under the direction of the SAR ADC high-level matching and energy models proposed previously by the applicant, a novel D/A conversion network combined a full unit-capacitor array with an intermittent-sleeping resistor ladder and a low power logic circuit based on self-control are presented for optimizing the matching performance and the power of the SAR ADCs. Furthermore, the time-interleaved technique is used to improve the sampling rate of the SAR A/D converter. The high-level system models of the time-interleaved SAR ADC are given to reflect the influences of the key component mismatch and the channel mismatch in bandwith, timing, gain, offset and nonlinearity to the performance of the time-interleaved SAR ADC. Based on the direction of the high-level system models proposed, the optimization techniques about the matching performance and the power for the time-interleaved SAR ADC are realized in the nanoscale CMOS process. The
英文关键词: analog-to-digital converter;successive approximation register;high-level model;time-interleaving;low power