AutoModel: Automatic Synthesis of Models from Communication Traces of SoC Designs

Modeling system-level behaviors of intricate System-on-Chip (SoC) designs is crucial for design analysis, testing, and validation. However, the complexity and volume of SoC traces pose significant challenges in this task. This paper proposes an approach to automatically infer concise and abstract models from SoC communication traces, capturing the system-level protocols that govern message exchange and coordination between design blocks for various system functions. This approach, referred to as model synthesis, constructs a causality graph with annotations obtained from the SoC traces. The annotated causality graph represents all potential causality relations among messages under consideration. Next, a constraint satisfaction problem is formulated from the causality graph, which is then solved by a satisfiability modulo theories (SMT) solver to find satisfying solutions. Finally, finite state models are extracted from the generated solutions, which can be used to explain and understand the input traces. The proposed approach is validated through experiments using synthetic traces obtained from simulating a transaction-level model of a multicore SoC design and traces collected from running real programs on a realistic multicore SoC modeled with gem5.