Real-time and cyber-physical systems need to interact with and respond to their physical environment in a predictable time. While multicore platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability. Large fluctuations in latency to access data shared between multiple cores is an important contributor to the overall execution-time variability. In addition to the temporal unpredictability introduced by caching, parallel applications with data shared across multiple cores also pay additional latency overheads due to data coherence. Analyzing the impact of data coherence on the worst-case execution-time of real-time applications is challenging because only scarce implementation details are revealed by manufacturers. This paper presents application level control for caching data at different levels of the cache hierarchy. The rationale is that by caching data only in shared cache it is possible to bypass private caches. The access latency to data present in caches becomes independent of its coherence state. We discuss the existing architectural support as well as the required hardware and OS modifications to support the proposed cacheability control. We evaluate the system on an architectural simulator. We show that the worst case execution time for a single memory write request is reduced by 52%. Benchmark evaluations show that proposed technique has a minimal impact on average performance.
翻译:实时和网络物理系统需要与实时和网络物理系统互动,并在可预见的时间里对其物理环境作出反应。虽然多核心平台提供了令人难以置信的计算能力和吞吐量,但它们也引入了新的不可预测性来源。获取多个核心之间共享的数据的悬浮性波动是整个执行时间变化的一个重要因素。除了通过缓存带来的时间不可预测性外,与多个核心之间共享数据的平行应用也由于数据的一致性而支付额外的延缓性管理费。分析数据一致性对实时应用最坏情况执行时间的影响具有挑战性,因为制造商只披露了极少的执行细节。本文为缓存层结构不同层次的缓存数据提供了应用级别的控制。其理由是,只通过在共享缓存中缓存数据,就有可能绕过私人缓存。对缓存中的数据的存时间变得独立于其一致性状态。我们讨论了现有的建筑支持以及为支持拟议的缓存控制所需的硬件和操作系统修改。我们评估了建筑模拟器的系统。我们显示,对于单一记忆基准要求的最小执行时间是最小的。我们显示一个最小的运行时间,通过一个最小的存储基准要求显示一个最小的运行要求。