Compiling high-level programs to target high-speed packet-processing pipelines is a challenging combinatorial optimization problem. The compiler must configure the pipeline's resources to match the high-level semantics of the program, while packing all of the program's computation into the pipeline's limited resources. State of the art approaches tackle individual aspects of this problem. Yet, they miss opportunities to efficiently produce globally high-quality outcomes. We argue that High-Level Synthesis (HLS), previously applied to ASIC/FPGA design, is the right framework to decompose the compilation problem for pipelines into smaller pieces with modular solutions. We design an HLS-based compiler that works in three phases. Transformation rewrites programs to use more abundant pipeline resources, avoiding scarce ones. Synthesis breaks complex transactional code into configurations of pipelined compute units. Allocation maps the program's compute and memory to the hardware resources. We prototype these ideas in a compiler, CaT, which targets the Tofino pipeline and a cycle-accurate simulator of a Verilog hardware model of an RMT pipeline. CaT can handle programs that existing compilers cannot currently run on pipelines, generating code faster than existing compilers, while using fewer pipeline resources.
翻译:将高层次程序归并到高速度的包处理管道上是一个具有挑战性的组合优化问题。 编译者必须配置管道资源, 以匹配程序高层次的语义, 同时将程序的所有计算方法包装在管道的有限资源中。 艺术状态方法解决了这一问题的个别方面。 然而, 他们错过了高效生产全球高质量结果的机会。 我们认为, 高级合成(HLS)(HLS) (HLS) (HLS) (HLS) (HLS) (以前适用于ACIC/FGA 设计) 是将管道的编译问题分解为模块化解决方案的小部分的正确框架。 我们设计了基于HLS(HLS) (H) 的编译程序, 以三个阶段为基础。 转换重写程序, 使用更丰富的管道资源来使用更丰富的管道资源, 综合复杂的交易代码到编译管道单位的配置中。 我们将这些想法原型的CAT(CAT) (HAFI) (H) (H) (HLS) (H) (HL) (HLS) (H) (HLS) (H) (HL) (HL) (H) (H) (H) (HT) (H) (H) (H) (H) (H) (H) (H) (HT) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (H) (