Applications with low data reuse and frequent irregular memory accesses, such as graph or sparse linear algebra workloads, fail to scale well due to memory bottlenecks and poor core utilization. While prior work with prefetching, decoupling, or pipelining can mitigate memory latency and improve core utilization, memory bottlenecks persist due to limited off-chip bandwidth. Approaches doing processing in-memory (PIM) with Hybrid Memory Cube (HMC) overcome bandwidth limitations but fail to achieve high core utilization due to poor task scheduling and synchronization overheads. Moreover, the high memory-per-core ratio available with HMC limits strong scaling. We introduce Dalorex, a hardware-software co-design that achieves high parallelism and energy efficiency, demonstrating strong scaling with >16,000 cores when processing graph and sparse linear algebra workloads. Over the prior work in PIM, both using 256 cores, Dalorex improves performance and energy consumption by two orders of magnitude through (1) a tile-based distributed-memory architecture where each processing tile holds an equal amount of data, and all memory operations are local; (2) a task-based parallel programming model where tasks are executed by the processing unit that is co-located with the target data; (3) a network design optimized for irregular traffic, where all communication is one-way, and messages do not contain routing metadata; (4) novel traffic-aware task scheduling hardware that maintains high core utilization; and (5) a data placement strategy that improves work balance. This work proposes architectural and software innovations to provide the greatest scalability to date for running graph algorithms while still being programmable for other domains.
翻译:低数据再利用和经常不定期的内存访问的应用,如图表或稀疏线性代数工作量,由于记忆瓶颈和核心利用率低,未能很好地缩小规模。虽然先前的预发、脱钩或管状设计工作可以减轻记忆延缓度,提高核心利用率,但记忆瓶颈仍然存在,原因是离芯带带带带宽有限。与混合内存立管(HMC)进行模拟(PIM)处理的方法克服了带宽限制,但由于任务时间安排和同步管理不当,未能实现高核心利用率。此外,由于HMC的记忆瓶颈和核心利用率低,现有高记忆-核心核心比核心比核心比高。我们引入Dalorolex,硬件-软件共同设计共同设计,实现高平行和能效,在处理图形和细微的平流中显示超过16,000个核心的缩略图和细微的平流动。在PIML工作之前,Dalorex改进了业绩和能源消耗,在以下两个级别上达到两个级别:(1)基于平台的分布式和缩式结构结构结构,每个处理数据时,每个处理数据数量相等的数据、运行数据、所有存储系统操作都是最接近的运行和最稳定的轨道;(2) 在设计中,在设计中,一个核心任务周期中,一个轨道上进行一个核心任务安排,而最平行的工作是同步的轨道,一个同步的计算。