Datacenter servers are increasingly heterogeneous: from x86 host CPUs, to ARM or RISC-V CPUs in NICs/SSDs, to FPGAs. Previous works have demonstrated that migrating application execution at run-time across heterogeneous-ISA CPUs can yield significant performance and energy gains, with relatively little programmer effort. However, FPGAs have often been overlooked in that context: hardware acceleration using FPGAs involves statically implementing select application functions, which prohibits dynamic and transparent migration. We present Xar-Trek, a new compiler and run-time software framework that overcomes this limitation. Xar-Trek compiles an application for several CPU ISAs and select application functions for acceleration on an FPGA, allowing execution migration between heterogeneous-ISA CPUs and FPGAs at run-time. Xar-Trek's run-time monitors server workloads and migrates application functions to an FPGA or to heterogeneous-ISA CPUs based on a scheduling policy. We develop a heuristic policy that uses application workload profiles to make scheduling decisions. Our evaluations conducted on a system with x86-64 server CPUs, ARM64 server CPUs, and an Alveo accelerator card reveal 88%-1% performance gains over no-migration baselines.
翻译:数据中心服务器日益多样化:从x86主机CPU, 到ARM-TRek, 到NICs/SSDs的ARM 或RISC-V CPU, 到FPGAs。 先前的工程已经表明, 异式ISA CPU的自动应用执行可带来显著的性能和能源增益, 而程序员的努力相对较少。 但是, 在这方面, FPGAs 常常被忽视: 使用 FPGAs 的硬件加速使用硬件加速应用功能, 禁止动态和透明的迁移。 我们介绍了 Xar- Trek, 一个新的编译和运行时段软件框架, 克服了这一限制。 Xar- Trek 编译了多个CPU ISA的应用程序, 并选择了加速运行的应用程序功能功能, 在运行时, MIAPS 和 FPGAs 之间执行移动时间监测服务器的工作量和将应用程序功能迁移到FPGA或基于调度政策的混合-ISA CPUs 。 我们开发了一种超常量性政策, 应用应用了应用工作量配置任务配置程序, CD- 86, 我们的业绩评估了C- PO- serma 。