多核异步数据触发微处理器设计关键技术研究

项目名称： 多核异步数据触发微处理器设计关键技术研究

项目编号： No.60873015

项目类型： 面上项目

立项/批准年度： 2009

项目学科： 无线电电子学、电信技术

项目作者： 王志英

作者单位： 中国人民解放军国防科学技术大学

项目金额： 37万元

中文摘要： 目前微处理器已经发展到多核时代，但是多核处理器的功耗是很难解决的问题。异步集成电路具有功耗低、无时钟偏移、电磁兼容性好、模块化和可重用性好等一系列优势。本课题针对异步多核数据触发微处理器设计关键技术展开了研究，取得了如下成果：1）提出了一种粗粒度的数据驱动异步电路设计方法和基于宏单元的异步电路设计自动化流程；2）提出了异步数据触发的思想，设计实现了一款异步数据触发微处理器；3）研究了多核异步触发体系结构，提出了一种基于层次位线缓冲结构的高性能低功耗片上路由器结构和一种混合编程模型，设计实现了一款多核异步数据触发微处理器原型系统；4）提出了一种多核异步微处理器功耗评估模型，并对原型系统的功耗特性进行了评估；5）研究了多核异步微处理器性能评估和优化方法，提出了一种数据驱动异步电路性能分析技术并建立了多核异步微处理器性能分析模型。本课题将异步电路技术与数据触发体系结构以及多核体系结构有机结合，设计实现了异步多核微处理器原型并在异步片上网络、多核异步处理器功耗和性能的评估优化方法等方面取得了突破，为低功耗多核处理器的设计实现奠定了理论和技术基础。

中文关键词： 异步电路；多核；数据触发；片上网络；功耗评估模型

英文摘要： Nowadays the microprocessor has developed into the multi-core era, but the power dissipation remains the difficult problem to resolve. Asynchronous integrated circuit has advantages in low power dissipation, no clock-skew, better electromagnetic comp- atibility, modularization and reusability, etc. This project focuses on the research of key techniques in asynchronous multi-core data triggered microprocessor design. The main research results include: 1) We propose a coarse-grained data-driven asynchronous circuit design method and a novel automated flow for asynchronous circuit design based on macro- cell; 2) We present the idea of asynchronous data-triggered architecture, and implement an asynchronous data-triggered microprocessor; 3) We study the asynchronous multi-core data-triggered architecture and implement a prototype of multi-core asynchronous data- triggered microprocessor; We propose a unified buffer structure (UBS) with hierarchical bit-line buffer and design a novel asynchronous on-chip router with high performance and low power dissipation.4) We propose an evaluation model for the power dissipation of asynchronous multi-core microprocessor and evaluate the feature of the prototype's power dissipation; 5) We study the evaluation and optimization method for the multi-core asynchronous microprocessor and propose analytic techniques for the performance of data-triggered asynchronous circuit. An analytic model for the performance of the multi-core asynchronous microprocessor has been built. This project combines the techniques of asynchronous circuit design and the data-triggered architecture and the multi-core architecture. A prototype of asynchronous multi-core microprocessor is design- ed and implemented. It makes breakthroughs in asynchronous on-chip network, multi-core asynchronous microprocessor and the evaluation and optimization methods of power diss- pation and performance. All these research achievements of the project contribute to theoretical and technical basis for the further design and implementation of low-power asynchronous multi-core microprocessor.

英文关键词： asynchronous circuits;multi-core microprocessor;data triggered architecture;network-on-chip;power estimation model