项目名称: 多核微处理器体系结构级容软错误设计与评估关键技术研究
项目编号: No.61202123
项目类型: 青年科学基金项目
立项/批准年度: 2013
项目学科: 计算机科学学科
项目作者: 龚锐
作者单位: 中国人民解放军国防科学技术大学
项目金额: 24万元
中文摘要: 本课题围绕多核微处理器体系结构级容软错误设计与评估展开研究,探索利用多核微处理器自身的丰富资源实现容软错误的可行性,通过体系结构进步带来的优势合理高效地应对制造工艺进步带来的软错误挑战。本课题将着力解决多核微处理器体系结构级容软设计中如何合理利用和如何量化评估两大关键科学问题。合理利用是指本课题将研究如何合理利用多核微处理器中丰富的资源,在少增加甚至不增加面积、性能、功耗开销的前提下,通过体系结构级设计有效地提高微处理器的可靠性。本课题将探索可重构的三核冗余执行模型来利用冗余的内核资源,探索硬件IO srcub技术来利用空闲的时间资源,探索基于扫描链的复位技术来利用已有的硬件结构,从而实现体系结构级容软错误设计。量化评估是指本课题将研究建立包括面积、性能、功耗维度在内的微处理器可靠性量化评估指标和框架,以便对微处理器容软错误能力进行更加准确的量化,从而有效地指导设计折中与设计选择。
中文关键词: 多核微处理器;可靠性;容软错误设计;可靠性量化评估;
英文摘要: This project focuses on the researches of architecture level design and evaluation for soft errors on multi core microprocessor. We will explore the feasibility of using the rich amount of resources in multi core microprocessor for soft error tolerance design. The goal of this project is to use the advantages brought by the development of microprocessor architecture to efficiently solve the threat of soft errors brought by the development of integrated circuit manufacture. This project will solve two key science problems in soft error tolerance design and evaluation on multi core microprocessors. One of the two problems is how to efficiently use the large amount of resources in multi core microprocessors in architecture level to achieve soft error tolerance with less or no extra overhead on area, performance and/or power. The three core redundant execution model will be proposed to use the redundant core resources, the hardware IO scrub technology to use the spare time resource, and a novel reset technology based on scan chain to use the existing hardware structure. The other of the two problems is how to quantitatively evaluate the reliability considering the overhead of area, performance and power. The novel quantitative evaluation metric and framework based on area, performance and power will be proposed in t
英文关键词: multicore microporcessor;reliability;soft error tolerant design;reliability quantitative evaluation;