面向众核处理器的HEVC并行编码关键技术研究

项目名称： 面向众核处理器的HEVC并行编码关键技术研究

项目编号： No.61472203

项目类型： 面上项目

立项/批准年度： 2015

项目学科： 计算机科学学科

项目作者： 颜成钢

作者单位： 清华大学

项目金额： 20万元

中文摘要： 高效能视频编码(High Efficient Video Coding, HEVC)是新一代视频编码标准，HEVC编码器复杂度是H.264编码器的三倍以上，传统的单处理器已经无法满足HEVC编码器实时运行的计算能力要求。本项目拟开展面向众核处理器的HEVC并行编码关键技术研究，重点研究适用于众核处理器的并行HEVC帧内预测和HEVC运动估计方法，以有效解决现有方法并行处理效率低和影响率失真性能的问题，在保证率失真性能的情况下提高并行处理效率：（1）针对HEVC帧内预测方法，首先用基于前向无环图的顺序并行处理编码块，再用支持向量机(support vector machine, SVM)选择最优编码块尺寸；（2）针对HEVC运动估计方法,首先在每个编码块内部采用改进的局部并行方法，然后当并行度太小的时候，并行处理完全独立编码块和部分独立编码块。

中文关键词： 众核处理器；HEVC；帧内预测；运动估计；并行处理效率

英文摘要： HEVC is the state-of-the-art video coding standard. HEVC encoders are expected to be several times more complex than H.264. Single-core processor can't provide powerful computing ability for HEVC encoder. In the project, we carry out the research on key techniques for parallel HEVC on many-core processor, which focus on parallel HEVC intra prdecition and HEVC motion estimation. Our method wants to make full use of the computing power of many-core processor and provides continuous powerful computing ability for the development of video coding, which efficiently resolves the problem of low rate-distortion performance and parallel processing performance in existing methods: (1) For HEVC intra prediction. firstly use the directed acyclic graph (DAG)-based order to parallelize coding blocks,then use the support vector machine (SVM) to select the optimal size of the coding block. (2) For HEVC motion estimation. firstly adopt improved LPM within each coding blocks. When the degree of parallelism is low, we process the completely independent blocks and partially independent blocks.

英文关键词： many-core processor；HEVC；intra prdecition；motion estimation；parallel processing performance