近阈值电源电压全数字锁相环理论及电路实现研究

项目名称： 近阈值电源电压全数字锁相环理论及电路实现研究

项目编号： No.61504061

项目类型： 青年科学基金项目

立项/批准年度： 2016

项目学科： 无线电电子学、电信技术

项目作者： 王子轩

作者单位： 南京邮电大学

项目金额： 21万元

中文摘要： 降低电源电压是实现超低功耗全数字锁相环（ADPLL）最直接而有效的途径，研究近阈值电源电压ADPLL具有重要的实用价值。降低电源电压使ADPLL电路在信号幅度、抗PVT性能及电路速度等方面受到极大的限制，进而影响环路的相位噪声性能。为解决上述关键问题，本课题拟对近阈值电源电压ADPLL的理论及实现进行研究。提出一种适用于低电压环境的数控振荡器方案，采用自举型缓冲器放大输出信号幅度，以提高环路带外噪声性能。提出一种含边沿切换电路的随机时间-数字转换器方案，利用动态匹配原理，在保证低功耗的同时将量化分辨率提高一倍，将环路带内噪声性能优化6dBc/Hz。提出一种适用于低电压环境的高速分频器方案，采用基于扩展型真单相钟控电路的预分频器结合动态阈值技术，提高电路的速度及可靠性。基于上述研究，本课题将建立一套低电压ADPLL的设计理论和方法，并以流片的方式验证和完善所研究的理论和相关技术。

中文关键词： 锁相环(PLL)；频率综合器（PLL）；压控振荡器(VCO)；相位噪声；分频器

英文摘要： Reducing voltage supply is the most straightforward and effective method to implement ultra-low-power all digital phase locked-loops (ADPLLs). The research on ADPLLs under near-threshold voltage supply has important practice value. Reducing voltage supply largely limits ADPLLs in signal amplitude, the tolerance toward PVT variations and circuit speed, and further deteriorates the performance of phase noise. In order to solve these key problems, this subject will research the theory and implementation of ADPLLs under near-threshold voltage supply. A digitally controlled oscillator scheme that is appropriate for low-voltage is proposed. The scheme employs a bootstrapped buffer to amplify output signal amplitude and to enhance the performance of out-band phase noise. A stochastic time-to-digital converter scheme with edge-interchanging circuit is proposed, which uses the theory of dynamic element matching to improve the quantization resolution by a factor of 2 and to achieve low-power design simultaneously. The scheme improves the in-band phase noise by 6dBc/Hz. A high-speed divider scheme that is appropriate for low-voltage is proposed. It uses a 2/3 prescaler based on extended true single-phase-clock circuit and dynamic threshold technique to improve the circuit speed and reliability. Based on the aforementioned research, this subject will build an ADPLL design theory and method under low-voltage, and will also testify and perfect the theory and the relative techniques based on tape-out.

英文关键词： Phase-locked loop;Frequency synthesizer; Voltage-controlled oscillator;Phase noise;Divider