项目名称: SEU故障的系统级容错加固技术研究
项目编号: No.61472260
项目类型: 面上项目
立项/批准年度: 2015
项目学科: 自动化技术、计算机技术
项目作者: 张伟功
作者单位: 首都师范大学
项目金额: 80万元
中文摘要: 研究采用纳米级工艺制造面向空间应用的高性能微处理器具有重要的战略意义和现实需求。空间环境下,单粒子事件会引起微处理器电路的数据与状态翻转(SEU)故障,需要在系统级和电路级采用容错加固措施才能保证微处理器的工作可靠性。随着特征尺寸减小和工作电压降低,纳米级电路中SEU故障的发生机率大大增加,且不再仅仅引起单个数据位翻转,而是最多可同时引起8位翻转。以EDAC、TMR、奇偶校验为代表的容错方法已无法满足要求,研究探索新的能够对多位错误进行快速高效容错的算法已成为纳米级微处理器发展必须解决的重要科学问题之一。本项目以流水线和存储部件为研究对象,提出一种自修复双冗余流水线结构和一种快速BCH混合纠检错方法,研究高性能微处理器多位SEU故障的系统级容错加固方法,与器件级加固措施结合,不仅可以消除空间环境下SEU故障对微处理器的危害,提高可靠性,还可降低资源需求,提高处理器工作速度。
中文关键词: SEU容错;纳米工艺;微处理器;流水线;BCH
英文摘要: Research on high-performance nano processors has important strategic significance and great application needs. For the processor working in radiation environment in space, it is easy to cause the single event effect(SEE) on circuits and the system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue, and need system-level and circuit-level harden schemes to ensure the reliability. However, as the technology and voltage scaling, single event upset(SEU) not only inevitably increase single bit faults, but also trigger Multiple Bit Upset (MBU), which has been a serious problem about reliability in nano technology. The state of the art fault -tolerant schemes, such as EDAC, TMR and parity, are insufficient to stem the growing multi-bits error. Accordingly, explore effective fault-tolerant schemes to recover multi-bits faults has become an important scientific issue for nano microprocessor research. To this end, we plan to explore the following research tasks in this proposal: we focus on the pipeline and storage unit, propose a novel self-recovery of dual-pipeline structure and a fast BCH-embedded parallel error correct scheme. In addition to circuit-level harden strategy,research on system-level harden strategy towards MBU for high-performance microprocessor,will improve system reliability, reduce resource requirements, and improve performance as well.
英文关键词: Fault Tolerance on SEU;Nano technology;Microprocessor;Pipeline;BCH