Preface
1. Evolution of 1-D, 2-D, and 3-D Lifting Discrete Wavelet Transform VLSI Architecture
C. S. N. Koushik, Abhishek Choubey, Shruti Bhargava Choubey, and D. Naresh
2. Execution of Lifting-Scheme Discrete Wavelet Transform by Canonical Signed Digit Multiplier
Gundugonti Kishore Kumar and Narayanam Balaji
3. Radix-8 Booth Multiplier in Terms of Power and Area Efficient for Application in the Field of 2D DWT Architecture
Gundugonti Kishore Kumar and Narayanam Balaji
4. Design and Performance Evaluation of Energy Efficient 8-Bit ALU at Ultra Low Supply Voltages Using FinFET with 20nm Technology
Vallabhuni Vijay, Pittala Chandra Shekar, Shaik Sadulla, Putta Manoja, Rallabhandy Abhinaya, Merugu Rachana, and Nakka Nikhil
5. Design and Statistical Analysis of Strong Arbiter PUFs for Device Authentication and Identification
Kurra Anil Kumar and Usha Rani Nelakuditi
6. An Impact of Aging on Arbiter Physical Unclonable Functions
Kurra Anil Kumar and Usha Rani Nelakuditi
7. Advanced Power Management Methodology for SoCs Using UPF
Usha Rani Nelakuditi, Naveen Kumar Challa, and K. Anil Kumar
8. Architecture Design: Network-on-Chip
N. Ashok Kumar, A. Kavitha, P. Venkatramana, and Durgesh Nandan
9. Routing Strategy: Network-on-Chip Architectures
N. Ashok Kumar, S. Vishnu Priyan, P. Venkatramana, and Durgesh Nandan
10. Self-Driven Clock Gating Technique for Dynamic Power Reduction of High-Speed Complex Systems
Roopa R. Kulkarni and S. Y. Kulkarni
11. Optimization of SoC Sub-Circuits Using Mathematical Modeling
Magnanil Goswami
12. An Efficient Design of D Flip Flop in Quantum-Dot Cellular Automata (QCA) for Sequential Circuits
Birinderjit Singh Kalyan, Harpreet Kaur, Khushboo Pachori, and Balwinder Singh
13. Design and Performance Analysis of Digitally Controlled DC-DC Converter
Subhransu Padhee, Madhusmita Mohanty, and Ambarish Panda
Index
第一章讨论了小波变换将图像表示为可积平方函数的重要性,它可以经常用于医疗和汽车行业或任何领域的图像使用。本章涵盖了各种类型的小波变换,其中每种类型可以是单一的或多层次的设计架构。本章涵盖了各种方案,如提升、翻转、卷积等,以分析在一定吞吐量率下的结果。它涵盖了如何设计具有尖锐截止频率的滤波器在从图片中去除不必要的元素中发挥主要作用。
第二章讨论了乘法器的效率,它对设备的功能有重要的影响,特别是在信号处理和本章讨论。在SOPOT体系结构中,省略了不必要的移位器和多路复用器,提出了新的“标准符号数字(CSD)”表示,并降低了寄存器维数。
第三章介绍了一个改进的2D-DWT架构的16位Booth乘法器。在这个工作中,不需要生成所有的局部产品;只有系数所要求的必要产物是充分的。可以观察到,在执行执行过程中,建议的体系结构比现有体系结构需要更少的时钟周期,从而提高了速度。为了与有效结果进行比较,本文提出的方法、CSD和Booth乘法器在Cadence Genus 90 nm技术中使用Verilog HDL进行合成。
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