Graph pattern mining applications try to find all embeddings that match specific patterns. Compared to the traditional graph computation, graph mining applications are computation-intensive. The state-of-the-art method, pattern enumeration, constructs the embeddings that match the pattern. The key operation -- intersection -- of two edge lists, poses challenges to conventional architectures and requires substantial execution time. In this paper, we propose IntersectX, a vertically designed accelerator for pattern enumeration with stream instruction set extension and architectural supports based on conventional processor. The stream based ISA can be considered as a natural extension to the traditional instructions that operate on scalar values. We develop the IntersectX architecture composed of specialized mechanisms that efficiently implement the stream ISA extensions, including: (1) Stream Mapping Table (SMT) that records the mapping between stream ID and stream register; (2) the read-only Stream Cache (S-Cache) that enables efficient stream data movements; (3) tracking the dependency between streams with a property of intersection; (4) Stream Value Processing Unit (SVPU) that implements sparse value computations; and (5) the nested intersection translator that generates micro-op sequences for implementing nested intersections. We implement IntersectX ISA and architecture on zSim, and test it with seven popular graph mining applications (triangle/three-chain/tailed-traingle counting, 3-motif mining, 4/5-clique counting, and FSM) on ten real graphs. We develop our own implementation of AutoMine (InHouseAutomine). The results show that IntersectX significantly outperforms InHouseAutomine on CPU, on average 10.7 times and up to 83.9 times ; and GRAMER, a state-of-the-art graph pattern mining accelerator, based on exhaustive check, on average 40.1 times and up to 181.8 times.
翻译:图形模式采矿应用程序试图找到所有符合特定模式的嵌入。 与传统图形计算相比, 图形采矿应用程序是计算密集型的。 最先进的方法, 模式查点, 构建符合模式的嵌入。 关键操作 -- -- 交叉 -- -- 两个边缘列表, 给常规架构带来挑战, 需要大量执行时间。 在本文中, 我们提议了Intercontexx, 一个垂直设计的用于以传统流程处理器为基础进行模式查勘的加速器。 基于 ISA 的流是一个自然扩展, 与使用 斯卡勒 值运行的传统指令相匹配。 我们开发了由专门机制组成的IntercontroleX 架构架构, 高效执行 ISA 的流程扩展。 (1) Stream 映像表(SM) 记录了流标识和流登记册之间的映像; (2) 仅读的Stache (S- Cachelex) 数据移动; (3) 跟踪流与交叉的属性之间的依赖; (4) Stream- dol- creal 处理器股股(S- cloade) 用于进行稀释的计算; 以及 AS- breal- breal- breal- deal- deal- deal- deal- deal A) 时间。