Due to the limitations of realizing artificial neural networks on prevalent von Neumann architectures, recent studies have presented neuromorphic systems based on spiking neural networks (SNNs) to reduce power and computational cost. However, conventional analog voltage-domain integrate-and-fire (I&F) neuron circuits, based on either current mirrors or op-amps, pose serious issues such as nonlinearity or high power consumption, thereby degrading either inference accuracy or energy efficiency of the SNN. To achieve excellent energy efficiency and high accuracy simultaneously, this paper presents a low-power highly linear time-domain I&F neuron circuit. Designed and simulated in a 28nm CMOS process, the proposed neuron leads to more than 4.3x lower error rate on the MNIST inference over the conventional current-mirror-based neurons. In addition, the power consumed by the proposed neuron circuit is simulated to be 0.230uW per neuron, which is orders of magnitude lower than the existing voltage-domain neurons.
翻译:由于在流行的 von Neumann 建筑中实现人工神经网络的局限性,最近的研究介绍了以跳动神经网络为基础的神经形态系统,以减少动力和计算成本,然而,基于当前镜片或副镜片的常规模拟电压-磁内集成-火(I & F)神经电路,造成严重问题,如非线性或高电能消耗,从而降低SNN的推导精度或能效。为了同时实现极高的能效和高精度,本文件展示了一种低功率高线性时空 I & F神经电路。在28nm CMOS 工艺中设计和模拟的,拟议的神经电路导致MNIST对常规的当前镜状神经的推断误差率超过4.3x。此外,拟议的神经电路消耗的电量被模拟为每神经元0.230uW,其规模低于现有的电压-多功能神经元。