To increase the science rate for high data rates/volumes, Thomas Jefferson National Accelerator Facility (JLab) has partnered with Energy Sciences Network (ESnet) to define an edge to data center traffic shaping / steering transport capability featuring data event-aware network shaping and forwarding. The keystone of this ESnet JLab FPGA Accelerated Transport (EJFAT) is the joint development of a dynamic compute work Load Balancer (LB) of UDP streamed data. The LB is a suite consisting of a Field Programmable Gate Array (FPGA) executing the dynamically configurable, low fixed latency LB data plane featuring real-time packet redirection at high throughput, and a control plane running on the FPGA host computer that monitors network and compute farm telemetry in order to make dynamic decisions for destination compute host redirection / load balancing.
翻译：为了增加高数据速率/卷的科学速率，托马斯杰斐逊国家加速器设施（JLab）与能源科学网络（ESnet）合作，定义了一种边缘到数据中心流量整形/定向传输能力，其特点是数据事件感知网络整形和转发。 ESnet JLab FPGA 加速传输（EJFAT）的关键是联合开发动态计算工作负载平衡器（LB）以处理 UDP 流数据。LB 是一个套件，包括执行动态配置的低固定延迟 LB 数据平面的 FPGA，其具有高吞吐量的实时数据包重定向能力，以及在 FPGA 主机计算机上运行的控制平面，该平面监视网络和计算农场遥测，以动态决定目标计算主机重定向/负载平衡。
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