Memristive in-memory sorting has been proposed recently to improve hardware sorting efficiency. Using iterative in-memory min computations, data movements between memory and external processing units can be eliminated for improved latency and energy efficiency. However, the bit-traversal algorithm to search the min requires a large number of column reads on memristive memory. In this work, we propose a column-skipping algorithm with help of a near-memory circuit. Redundant column reads can be skipped based on recorded states for improved latency and hardware efficiency. To enhance the scalability, we develop a multi-bank management that enables column-skipping for dataset stored in different memristive memory banks. Prototype column-skipping sorters are implemented with a 1T1R memristive memory in 40nm CMOS technology. Experimented on a variety of sorting datasets, the length-1024 32-bit column-skipping sorter with state recording of 2 demonstrates up to 4.08x speedup, 3.14x area efficiency and 3.39x energy efficiency, respectively, over the latest memristive in-memory sorting.
翻译:为了提高硬件分类效率,最近提议了模拟模拟分类法,以便提高硬件分类效率。使用迭代的模拟分钟计算,内存和外部处理器之间的数据移动可以消除,以提高潜值和能源效率。然而,搜索分钟的比特三角算法需要大量列读存储器。在这项工作中,我们提议了一个柱式跳动算法,并借助近模电路。重复的柱子读取可以根据记录状态跳过,以提高延度和硬件效率。为了提高可扩缩性,我们开发了多银行管理,以便能够对存储在不同内存库中的数据集进行柱式跳动。在40nm 的 CMOS 技术中,以 1T1R 的内存方式执行原型柱式排位排序器。在一系列排序数据集上进行了实验,长度 1024 32 位柱式跳动算法, 状态记录显示2 达到 4.08x 速度, 3.14x 节率和 3.39x 节能效率, 分别显示在最新的Mem 排序中。