In this paper, we present a multiplier based on a sequence of approximated accumulations. According to a given splitting point of the carry chains, the technique herein introduced allows varying the quality of the accumulations and, consequently, the overall product. Our approximate multiplier trades-off accuracy for a reduced latency (with respect to an accurate sequential multiplier) and exploits the inherent area savings of sequential over combinatorial approaches. We implemented multiple versions with different bit-width and accuracy configurations, targeting an FPGA and a 45nm ASIC to estimate resources, power consumption, and latency. We also present two error analyses of the proposed design based on closed-form analysis and simulations.
翻译:在本文中,我们根据相近的累积顺序提出一个乘数。根据承载链的某一分点,此处采用的技术允许改变累积质量和总产品的质量。我们估计的乘数交换精确度降低(精确的顺序乘数),利用相继组合法的内在节减面积。我们实施了多种版本,以不同的位宽和精确度配置为对象,以FPGA和45nm ASIC为对象,对资源、电耗和耐久性进行了估计。我们还根据封闭式分析和模拟对拟议的设计进行了两次错误分析。