千核级高性能、可容错无缓冲片上网络关键技术研究

项目名称： 千核级高性能、可容错无缓冲片上网络关键技术研究

项目编号： No.61303066

项目类型： 青年科学基金项目

立项/批准年度： 2014

项目学科： 自动化技术、计算机技术

项目作者： 冯超超

作者单位： 中国人民解放军国防科学技术大学

项目金额： 23万元

中文摘要： 片上网络（NoC）的出现，有效解决了大规模多核处理器的全局通信问题，提升了多核片上通信的性能。但是，随着集成度的不断提高，功耗和面积的日益增加成为制约多核处理器片上互连发展的重要因素；并且，特征尺寸的缩小、电源电压的降低以及时钟频率的提升严重影响片上网络的可靠性。因此，研究高能效、低开销、高可靠的无缓冲片上路由器对于千核级处理器片上互连的设计具有重要意义。 本项目围绕无缓冲路由器微体系结构的性能优化和可靠性设计展开，提出面向千核级处理器片上互连的低延迟、可容错无缓冲路由器体系结构。重点突破无缓冲路由器偏转路由算法的理论分析、低延迟无缓冲路由器结构设计、能够有效检测、处理瞬态故障与永久故障的完整无缓冲路由器容错体系结构以及基于偏转路由的低延迟、可容错无缓冲多播算法。研究成果将对国产多核众核微处理器设计起到重要的基础支撑作用。

中文关键词： 片上网络；无缓冲路由器；容错；偏转路由；多播

英文摘要： The emergence of Network-on-Chip (NoC) solves the global communication problem for the large scale multicore processors and improves the performance of the on-chip communication. However, with the enhancement of the integration degree, power consumption and area have already become a limiting constraint in the on-chip interconnection of multicore processors. In addition, shrinking feature size, lower power voltage and higher frequency have a negative impact on the reliability of NoC. Thus, energy-efficient, low-overhead and high reliable bufferless router is significant for the on-chip interconnection of thousands-core processors. This project investigates performance optimization and reliability design for the bufferless router microarchitecture. We break through the following techniques: a theoretic analysis method for deflection routing algorithm, a low latency bufferless router architecture, a complete fault-tolerant architecture including detecting and handling both transient and permanent faults for bufferless router, a low-latency and fault-tolerant multicast algorithm based on deflection routing. The research result of this project will build an important infrastructure for domestic multicore and manycore processor design.

英文关键词： Network-on-Chip；Bufferless Router；Fault-tolerance；Deflection Routing；Multicast