Increasing investment in computing technologies and the advancements in silicon technology has fueled rapid growth in advanced driver assistance systems (ADAS) and corresponding SoC developments. An ADAS SoC represents a heterogeneous architecture that consists of CPUs, GPUs and artificial intelligence (AI) accelerators. In order to guarantee its safety and reliability, it must process massive amount of raw data collected from multiple redundant sources such as high-definition video cameras, Radars, and Lidars to recognize objects correctly and to make the right decisions promptly. A domain specific memory architecture is essential to achieve the above goals. We present a shared memory architecture that enables high data throughput among multiple parallel accesses native to the ADAS applications. It also provides deterministic access latency with proper isolation under the stringent real-time QoS constraints. A prototype is built and analyzed. The results validate that the proposed architecture provides close to 100\% throughput for both read and write accesses generated simultaneously by many accessing masters with full injection rate. It can also provide consistent QoS to the domain specific payloads while enabling the scalability and modularity of the design.
翻译:计算机技术方面的投资和硅技术的进步刺激了先进驱动器援助系统(ADAS)和相应的 SoC开发的快速增长。ADAS SoC是一个由CPU、GPU和人工智能加速器组成的多种结构。为了保证其安全和可靠性,它必须处理从高清晰视频摄像机、雷达和利达尔等多种冗余来源收集的大量原始数据,以便正确识别对象并迅速做出正确的决定。一个特定域内存结构对于实现上述目标至关重要。我们提出了一个共同的记忆结构,使ADAS应用程序的多个本地平行存取者能够进行高数据通过量。它还在严格的实时QOS限制下提供了具有适当隔离性的确定性存留时间。一个原型已经建立并进行了分析。结果证实,拟议的结构为许多使用全注射率的硕士同时生成的读写存取提供了近100 ⁇ 的读取量。它还可以为域特定有效载荷提供一致的QOS,同时使设计具有可缩性和模块性。