纳米工艺下SoC电源/地网络分析及验证方法

项目名称： 纳米工艺下SoC电源/地网络分析及验证方法

项目编号： No.61274031

项目类型： 面上项目

立项/批准年度： 2013

项目学科： 无线电电子学、电信技术

项目作者： 蔡懿慈

作者单位： 清华大学

项目金额： 82万元

中文摘要： 集成电路进入纳米时代，电源/地网(P/G)电流增大、寄生效应显著和电压降容限降低，成为严重影响芯片性能、功耗和可靠性的设计瓶颈。SoC芯片规模和复杂度的增大，使电源/地网分析和验证面临规模、精度、效率和内存资源的巨大挑战，是业界研究和亟待解决的热点问题。本课题针对SoC中P/G设计存在的问题，深入研究P/G网络快速分析方法。从P/G结构、封装电感特性及求解问题规模入手，研究P/G电阻、电容和电感建模和约简方法，为提高分析效率和减少资源占用提供基础及指导；在此基础上深入研究P/G瞬态分析方法，通过对方程性态、频率响应和求解方法的研究，提高分析精度和效率；研究非向量输入P/G验证方法，在设计早期无法获得模块吸纳电流情况下，为供电系统设计提供参考依据；依据P/G结构特点和求解算法的特性，研究并行加速算法和策略，提高分析效率。课题将为SoC供电设计提供理论和算法支撑，具有重要理论研究和实用价值

中文关键词： 电源/地网络；分析及验证；纳米工艺；物理设计；集成电路

英文摘要： With the manufacturing technology has been into nanometer era, it ensures smaller size, higher integration and lower power consumption. Meanwhile, the significantly parasitic effects, the increasing design scale and the reducing voltage tolerance are making the analysis of power/ground (P/G) RLC network as bottleneck for very large scale SoC design. This will affect the chip performance, power consumption and yield which is a hot topic of both research area and industrial world. In order to ensure the robustness of power network on chip, we must solve the challenging problem of the P/G analysis of accuracy, run efficiency and memory consumption. This project will research the analysis methods of RLC network for large scale complex structure P/G network design. From the geometric structure of P/G network, package inductance parameters and problem characteristics, we study the P/G RLC modeling and reduction methods to provide a basis and guidance to improve analysis efficiency and resources consumption. And based on above we perform in-depth study on P/G transient analysis of equation of state of nature, frequency response and solving methods to improve the analysis performance which can reduce the time and space complexity without accuracy loss. We will also research vector-less verification methods for early sta

英文关键词： power grid；analysis and verification；nanometer technology；physical design；IC