异构众核处理器非对称片上互连网络研究

项目名称： 异构众核处理器非对称片上互连网络研究

项目编号： No.61502446

项目类型： 青年科学基金项目

立项/批准年度： 2016

项目学科： 自动化技术、计算机技术

项目作者： 刘少礼

作者单位： 中国科学院计算技术研究所

项目金额： 21万元

中文摘要： 在异构众核处理器的设计过程中，片上互连网络的设计是最主要的难点之一。目前，国内外学者的研究工作主要集中在传统同构众核处理器的对称均匀互连网络上，而对异构众核处理器上的互连网络研究还处于起步探索阶段。与同构众核核处理器片上互连网络不同，异构众核处理器的片上互连网络需要解决由于芯片结构不对称性带来的诸多问题。举例来说，由于芯片结构不对称，每个核上可以运行的应用程序会有较大差异，因此，不同处理器核或者加速器的访存通讯模式会大不相同，这对片上互连结构的设计在异构化，可扩展，以及低功耗三方面提出了新的挑战。本项目拟面向异构众核处理器片上互连结构设计的，以演化优化问题求解为依托，研究异构众核处理器片上互连结构设计的关键技术，力争形成异构众核处理器片上互连结构以及路由器结构设计的开源工具，为国产异构众核处理器设计提供支持。

中文关键词： 众核处理器；众核体系结构；异构多核处理器；片上网络

英文摘要： On-chip network architecture is one of the most important component of heterogeneous many-core processors. The previous works of researchers mainly focus on the uniform on-chip network architectures of homogeneous many-core processors, and there are only a few works about nonuniform on-chip network architectures. Be different from the uniform on-chip network architectures of homogeneous many-core processors, the nonuniform on-chip network architectures of heterogeneous many-core processors need to face the problems caused by the asymmetry of chip architecture. For example, due to the the asymmetry of chip architecture, the applications running on different cores will have a great difference, therefore, the memory access and communication behavior of different cores will also be very different. The difference of memory access and communication behavior will bring new challenges about isomerization, expandability, and low-power dissipation. This project plans to face the designing of the nonuniform on-chip network architectures of heterogeneous many-core processors, and takes the evolutionary optimal algorithms as basic tools, researches the key techniques of designing of nonuniform on-chip network architectures of heterogeneous many-core processors, develops the open source tools for nonuniform on-chip network architectures design, supports the developing of domestic many-core processors.

英文关键词： many-core processors;many-core architecture;heterogeneous many-core processors;network on-chip