一种面向频谱敏捷无线处理的空间阵列架构 (A Spatial Array for Spectrally Agile Wireless Processing)

Massive MIMO is a cornerstone of next-generation wireless communication, offering significant gains in capacity, reliability, and energy efficiency. However, to meet emerging demands such as high-frequency operation, wide bandwidths, co-existence, integrated sensing, and resilience to dynamic interference, future systems must exhibit both scalability and spectral agility. These requirements place increasing pressure on the underlying processing hardware to be both efficient and reconfigurable. This paper proposes a custom-designed spatial array architecture that serves as a reconfigurable, general-purpose core optimized for a class of wireless kernels that commonly arise in diverse communications and sensing tasks. The proposed spatial array is evaluated against specialized cores for each kernel using High-Level Synthesis (HLS). Both the reconfigurable and specialized designs are synthesized in a 32 nm process to assess latency, throughput, area, and power in realistic processes. The results identify conditions under which general-purpose systolic architectures can approach the efficiency of specialized cores, thereby paving the way toward more scalable and agile systems.

翻译：大规模MIMO是下一代无线通信的基石技术，在容量、可靠性和能效方面带来显著提升。然而，为满足高频段运行、宽带宽、多系统共存、一体化感知及动态干扰鲁棒性等新兴需求，未来系统必须兼具可扩展性与频谱敏捷性。这些要求对底层处理硬件提出了更高效率与可重构性的双重压力。本文提出一种定制化设计的空间阵列架构，作为可重构的通用核心，针对通信与感知任务中常见的一类无线核心运算进行优化。通过高层次综合（HLS）方法，将所提出的空间阵列与各核心运算的专用处理核进行对比评估。在32纳米工艺下对可重构设计与专用设计进行综合，以实际工艺条件评估其延迟、吞吐量、面积和功耗。结果表明，在特定条件下通用脉动阵列架构能够逼近专用处理核的效率，从而为构建更具可扩展性与敏捷性的系统奠定基础。