基于全局通信管理的NoC低功耗容错机制研究

项目名称： 基于全局通信管理的NoC低功耗容错机制研究

项目编号： No.61076019

项目类型： 面上项目

立项/批准年度： 2011

项目学科： 金属学与金属工艺

项目作者： 吴宁

作者单位： 南京航空航天大学

项目金额： 15万元

中文摘要： 针对片上网络通信可靠性设计问题，从解决数据传输中的瞬时故障和永久性故障两个层次，并结合功耗设计约束，重点研究了适用于NoC的低功耗容错机制及其实现方式。 课题根据容错NoC系统组成模块的通信特征，采用多元线性回归法建立了功耗与数据注入率、翻转率的关系，提出了一种基于宏模型的容错片上网络体系结构级功耗建模方法，有效提高了评估效率。结合NoC数据传输中的故障模型，提出了一种防串扰编码与差错控制编码的联合编码及低功耗检错重传方案，降低了串扰对传输链路的影响，实现了系统瞬时故障的检测和恢复。从全局通信管理的角度出发，提出了一种基于网络监控器的动态路由机制DyRS-NM，该机制基于网络监控器获取的全局网络实时状态信息，检测和定位NoC中的拥塞和故障链路，采用重传方式避免瞬时故障，通过重新路由计算绕开拥塞和永久性故障。综合上述全局可控的低功耗容错机制研究，实现了高性能高可靠性的NoC体系结构。 在此基础上，将低功耗容错机制研究从二维拓扑拓展到三维，提出了应用于三维拓扑的系统级延时与功耗评估模型，并依据该模型提出了一种延时与功耗优化的三维拓扑结构及其自适应路由算法，提高了系统高注入率情况下的吞吐量。

中文关键词： 片上网络；低功耗；串扰避免；容错机制；全局管理

英文摘要： Aiming at the problem of communication reliability design in Network on Chip (NoC), we focus on the research of low-power fault-tolerant scheme for NoC and its realization, from two aspects of solving the transient faults and permanent faults in data transmission joint with the design constraint of power consumption. According to the communication features of the key module in fault-tolerant NoC system, we apply a multiple linear regression method to build the relationship between injection rate , bit-flip of input data and power consumption, and propose a macro-model based fault-tolerant NoC architecture-level power modeling method, which achieves a significant improvement in evaluation speed. Joint with the fault model during data transmission in NoC, a joint coding scheme combined with crosstalk avoidance coding with error control coding and a low-power error detection and retransmission scheme are proposed. These shemes can reduce the impact of crosstalk on transmission link, and realize transient faults detection and recovery. From the perspective of the global communication management in NoC, a novel dynamic routing scheme based on Network Monitor called DyRS-NM is presented. The proposed scheme uses the network monitor to monitor overall network real-time conditions,and has the ability to discover and deal with both congestion and permanent faults and distinguish them from transient faults. DyRS-NM can avoid transient faults by using retransmission scheme, and also can detour congested and permanently faulted links by recalculating routing paths. From this research on global controlled low-power fault-tolerant schemes, the high performance and high reliabiliity NoC architecture is achieved. On this basis, we extend the research of low-power fault-tolerant scheme from the 2D to 3D topology, and the system-level delay and power evaluation model in 3D NoC topology is proposed.Then we propose a delay- and power- aware 3D NoC topology and a adaptive routing algorithm，which improve the throughput of system under high injection rate.

英文关键词： Network on Chip; low power; crosstalk avoidance; fault-tolerant scheme; global management